1. Field
Aspects of the present disclosure relate generally to voltage controlled oscillators (VCOs) and more specifically, to a low voltage, wide frequency range oscillator.
2. Background
In a conventional differential ring oscillator, the current output of each differential stage or cell generally takes a certain time to charge or discharge an input capacitance of the following stage to a threshold voltage. The differential stages are often coupled into a loop configuration such that, at a certain frequency, a 180 degrees phase shift may be imparted to signals travelling in the loop. If the loop gain is large enough, the signals become non-linear typically resulting in square wave oscillations.
Differential ring oscillators are widely used in mobile phones and other portable devices. In particular, differential ring oscillators are used in phase locked loops (PLLs) and in digital signal processors. Since mobile phones and other portable devices typically operate at a low voltage, PLLs in portable devices should also operate satisfactorily at a low voltage. Mobile phones and other portable devices also generally use batteries to supply their power. Thus, it is desirable that PLLs and other circuit components consume less power in order to increase efficiency and battery life. Because pseudo-differential ring oscillators consume less power than conventional differential ring oscillator for a given phase-noise performance, pseudo-differential oscillators are increasingly being used in mobile phones and other portable devices.
Advances in semiconductor fabrication technologies have increased the miniaturization of various integrated components. Nanometer-scaled electronics are now being used to implement such electronic components on a chip-level. However, nanometer technology operates at a lower voltage level than previous technology. Thus, a reduction of the minimum operating voltage will make pseudo-differential ring oscillators more suitable in such applications.
FIG. 1 shows a differential stage 100 of a pseudo-differential ring oscillator. It will be appreciated that a plurality of stages would be connected in a loop configuration to form a ring oscillator. The stage 100 includes first and second inverters 104 and 108 coupled between a voltage supply 106 and ground 110. The first inverter 104 comprises a P-channel transistor 116 and an N-channel transistor 120. The gates of the transistors 116 and 120 are interconnected to form an input node 150 to which an input signal Vin+ is applied. The drains of the transistors 116 and 120 are interconnected to form an output node 162. Responsive to the input signal Vin+, the first inverter 104 generates an output signal Vout− at the output node 162.
The second inverter 108 comprises a P-channel transistor 124 and an N-channel transistor 128 coupled between the voltage supply 106 and ground 110. The gates of the transistors 124 and 128 are interconnected to form a complementary input node 154 to which a complementary input signal Vin− is applied. The drains of the transistors 124 and 128 are interconnected to form a complementary output node 158. Responsive to the complementary input signal Vin−, the second inverter 108 generates a complementary output signal Vout+ at the complementary output node 158.
An N-channel latch 112 is coupled between the output 162 and the complementary output 158. The N-channel latch 112 comprises cross-coupled transistors 132 and 136. The gate of the transistor 132 is coupled to the drain of the transistor 136, and the gate of the transistor 136 is coupled to the drain of the transistor 132. Series connected capacitors 140 and 144 are coupled between the output node 162 and the complementary output node 158. The capacitors 140 and 144 interconnect at node 142, which can be used a secondary control node for the stage 100. While the N-channel latch 112 is illustrated in a half-latch configuration, it will be apparent to those skilled in the art that a full latch or a plurality of latches may be coupled between the output 162 and the complementary output 158.
The start-up of the stage 100 can be illustrated as follows. Assume Vt is the threshold voltage for all devices used in the stage 100. During start-up, the supply voltage, 106 is powered-up and increases from ground to a higher voltage level. As the supply voltage 106 is increased, the voltage on the output of the two inverters Vout+, Vout− tracks the supply voltage increase as k*Vsupply, where k is a factor determined by the leakage current ratios of PMOS and NMOS devices used in the design. For typical device sizing, k is usually about 0.5. In order for the ring to start oscillating, the latch 112 needs to be biased in a high-gain state so that the outputs of the two inverters are forced to be 180 degrees apart. This implies that the latch 112 input voltages, Vout+ and Vout−, should exceed Vt. Therefore, for a typical k=0.5, supply voltage should exceed 2Vt for the oscillator to start-up.
During oscillation, the operation of stage 100 can be explained as follows. In the initial operations, the input signal Vin+ is a signal having a value that is representative of the high state or as a logical 1 and the complementary input signal Vin− is a signal having a value that is represented as the low state or as a logical 0. Consequently, the P-channel transistor 116 is turned OFF, while the N-channel transistor 120 is turned ON. When Vin+ transitions to a logical 0, the N-channel transistor 120 is turned OFF, while the P-channel transistor 116 is turned ON, causing the output to switch to logical 1.
Referring now to the inverter 108, when the complementary input signal Vin− is a logical 0, the P-channel transistor 124 is turned ON, while the N-channel transistor 128 is turned OFF. Consequently, the complementary output signal Vout− becomes a logical 1. As the complementary input signal Vin− transitions to logical 1, the N-channel transistor 128 is turned ON, while the P-channel transistor 124 is turned OFF, causing the complementary output signal Vout− to become a logical 0.
Referring now to the N-channel latch 112, when the output signal Vout+ is a logical 1, the N-channel transistor 136 is turned ON, thereby pulling the complementary output Vout− to a logical 0. Consequently, the N-channel transistor 132 is turned OFF. When Vout− transitions to logical 1, the N-channel transistor 162 is turned ON, thereby pulling Vout+ to logical 0, which causes the transistor 136 to turn OFF. Thus, the N-channel latch 112 maintains a 180-degree phase shift between the output Vout+ and the complementary output Vout−.
It will be appreciated that the output frequency of a conventional pseudo-differential ring oscillator varies with the supply voltage 106. Since the minimum operating voltage is 2*Vt, the conventional pseudo-differential ring oscillator has a limited frequency range at its low-end. Further, since the amplitude of oscillation increases with the control voltage and thus, oscillation frequency, the frequency range is also limited at its high-end by an increasing oscillation amplitude.